Anomalous Response Times of Input Synchronizers

This paper deals with an anomalous behavior of input synchronizers which results in the occurrence of random errors in asynchronously interfaced synchronous digital systems. The errors are caused by the undefined response time of a flip-flop as it recovers from its metastable state. To obtain their frequency, the timing diagram of the flip-flops has been analyzed and the probability distribution of the anomalous response times has been measured. As an example, maximum response time of SN74S74 is estimated on the basis of a set of statistical measurements. The measurement technique presented may be used for any type of input synchronizer. Two well-known methods of reducing failure probability for SN74S74 are evaluated. Two fundamental solutions of the metastable-state problem in the clocked systems are described.