Title :
A 4H-SiC high power density VJFET as controlled current limiter
Author :
Tournier, D. ; Godignon, Ph. ; Montserrat, J. ; Planson, D. ; Raynaud, C. ; Chante, J.P. ; Sarrus, F. ; Bonhomme, C. ; de Palma, J.F.
Author_Institution :
Centro Nacional de Microelectron., UAB, Bellatera, Spain
Abstract :
Considering fault current limiters for serial protection, a number of structures exist, from regulation to other complex systems such as circuit breakers, mechanical switches or more conventional fuses. Up to now, only few semiconductor current limiter structures have been described in the literature. Although current regulative diode components already exist, the voltage and current capabilities (V/sub BR/=100 V I/sub max/=10 mA), do not allow their use in power systems. This paper presents both a simulation study and experimental results of a bi-directional current limiter structure based on a vertical SiC VJFET. This device was designed for serial protection in order to limit I/sup 2/t value. Finite-element simulations were performed with ISE-TCAD to design the device and evaluate static electrical characteristics of the VJFET. Dynamic simulations were performed to underline current reduction ability and power losses adjustment by gate resistance value optimization. Finally, electrical characterization for an unidirectional and a bi-directional devices has been carried out up to 400 V. The measured specific resistance is in the range of 176 m/spl Omega//spl middot/cm/sup 2/. Limiting capabilities have also been measured for a bi-directional device made of two unidirectional device connected head to tail. Highest breakdown voltage value in "current limiting state" were measured to be around to 811 V, corresponding to a high power density of 140 kW/cm/sup 2/.
Keywords :
fault current limiters; junction gate field effect transistors; power field effect transistors; power system faults; power system protection; semiconductor device measurement; semiconductor device models; semiconductor device testing; silicon compounds; 10 mA; 100 V; 400 V; 4H-SiC high power density VJFET; 811 V; H-SiC; bi-directional current limiter structure; breakdown voltage measurement; controlled current limiter; current reduction ability; dynamic simulations; electrical characterization; fault current limiters; finite element simulations; gate resistance value optimization; power losses adjustment; semiconductor current limiter structures; serial protection; specific resistance measurement; static electrical characteristics; Bidirectional control; Circuit breakers; Current limiters; Electric resistance; Electrical resistance measurement; Fault current limiters; Power semiconductor switches; Power system protection; Power system simulation; Switching circuits;
Conference_Titel :
Industry Applications Conference, 2002. 37th IAS Annual Meeting. Conference Record of the
Conference_Location :
Pittsburgh, PA, USA
Print_ISBN :
0-7803-7420-7
DOI :
10.1109/IAS.2002.1043845
