• DocumentCode
    383333
  • Title

    Performance limitation of sub-100-nm intrinsic-channel double-gate SOI MOSFETs

  • Author

    Omura, Yasuhisa ; Yanagi, Shin-ichiro

  • Author_Institution
    Dept. Electron., Kansai Univ., Osaka, Japan
  • fYear
    2002
  • fDate
    7-10 Oct 2002
  • Firstpage
    60
  • Lastpage
    61
  • Abstract
    The double-gate silicon-on-insulator MOSFET has been receiving world-wide attention as the device with the highest potential in the nano-scale regime. In this paper, we estimate the drive current of single-gate, conventional DG, and intrinsic channel IC-DG SOI devices by simulations, and we discuss the intrinsic performance of various SOI devices.
  • Keywords
    MOSFET; elemental semiconductors; nanoelectronics; semiconductor device models; silicon; silicon-on-insulator; 100 nm; IC-DG SOI devices; SOI devices; Si-SiO2; double-gate silicon-on-insulator MOSFET; drive current; intrinsic channel double-gate MOSFET; intrinsic performance; intrinsic-channel double-gate SOI MOSFETs; nano-scale regime; performance limitation; simulations; single-gate devices; MOSFETs; Semiconductor device modeling; Silicon; Silicon on insulator technology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, IEEE International 2002
  • Print_ISBN
    0-7803-7439-8
  • Type

    conf

  • DOI
    10.1109/SOI.2002.1044416
  • Filename
    1044416
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=383333