A precise sample-and-hold circuit topology in CMOS for low voltage applications with offset voltage self correction

Author

Ferreira, Luís Henrique C ; Moreno, Robson L. ; Pimenta, Tales C. ; Filho, Carlos A R

Author_Institution

Microelectron. Group, Univ. Fed. de Itajuba, Brazil

Volume

1

fYear

2002

fDate

2002

Firstpage

45

Abstract

This work describes a new topology for CMOS sample-and-hold circuits in low voltage with self-correction of the offset voltage caused by mismatches in the differential input pair of the operational amplifier. The charge injection of the NMOS switches, although not properly modeled by the simulators, is an important factor and it is minimized in this topology. The results were obtained using the ACCUSIM II simulator on the AMS CMOS 0.8 μm CYE and they reveal the circuit has a reduced error of just 0.03% at the output.

Keywords

CMOS analogue integrated circuits; circuit simulation; differential amplifiers; low-power electronics; operational amplifiers; sample and hold circuits; 0.8 micron; ACCUSIM II simulator; AMS CMOS 0.8 μm CYE; CMOS; charge injection; circuit error; differential input pair; low voltage applications; offset voltage self correction; operational amplifier; sample-and-hold circuit topology; Capacitors; Circuit simulation; Circuit topology; Low voltage; MOS devices; Operational amplifiers; Sampling methods; Semiconductor device modeling; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2002. 9th International Conference on

Print_ISBN

0-7803-7596-3

Type

conf

DOI

10.1109/ICECS.2002.1045329

Filename

1045329