A multiplierless decimation filter for ΣΔ A/D conversion

This paper describes the design of a FIR filter for decimation of signals coming from a multi-stage multi-bit ΣΔ modulator. The FIR digital filter is based on a multi-stage design with multiplier-free implementation, employing shifters and accumulators to implement power-of-two multiplications. Moreover, the number of shift operations in the whole filter is minimised, and clock frequency is reduced in any stage according to the corresponding sampling rate, in order to reduce power consumption and to avoid performance degradation due to crosstalk. The resulting architecture reduces area and power requirements with respect to multiplier-based solutions. Experimental results on integrated prototypes confirm the filter functionality and the estimated power consumption.