Introducing redundant transformations for high level built-in self-testable synthesis

Author

Yang, Laurence Tianruo ; Muzio, Jon

Author_Institution

Dept. of Comput. Sci., Saint Francis Xavier Univ., Antigonish, NS, Canada

Volume

2

fYear

2002

fDate

2002

Firstpage

475

Abstract

In our previous work (Proc. ICECS-01, vol. 1, pp. 549-552, 2001; Proc. SBCCI-01, pp. 115-121, 2001), we describe an integrated high-level synthesis algorithm for operation scheduling and data path allocation to facilitate built-in self-test designs. In this paper, we make use of two types of redundant transformations for the integrated synthesis algorithm, which add redundancy which improves test resources to be shared in the data path and operation scheduling. With a variety of benchmarks, we demonstrate the advantage of the approach by introducing redundant transformations compared with our previous and other conventional approaches.

Keywords

built-in self test; circuit CAD; design for testability; high level synthesis; integrated circuit design; integrated circuit testing; logic testing; processor scheduling; redundancy; BIST synthesis; built-in self-test designs; data path allocation; data path scheduling; high level built-in self-testable synthesis; integrated high-level synthesis algorithm; integrated synthesis algorithm; module allocation; operation scheduling; redundancy; redundant transformations; register allocation; shared test resources; Algorithm design and analysis; Automatic testing; Built-in self-test; Circuit testing; Computer science; High level synthesis; Performance evaluation; Processor scheduling; Resource management; Scheduling algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2002. 9th International Conference on

Print_ISBN

0-7803-7596-3

Type

conf

DOI

10.1109/ICECS.2002.1046201

Filename

1046201