DocumentCode :
3837668
Title :
Large-Scale SRAM Variability Characterization in 45 nm CMOS
Author :
Zheng Guo;Andrew Carlson;Liang-Teck Pang;Kenneth T. Duong;Tsu-Jae King Liu;Borivoje Nikolic
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA
Volume :
44
Issue :
11
fYear :
2009
Firstpage :
3174
Lastpage :
3192
Abstract :
Increased process variability presents a major challenge for future SRAM scaling. Fast and accurate validation of SRAM read stability and writeability margins is crucial for estimating yield in large SRAM arrays. Conventional SRAM read/write metrics are characterized through test structures that are able to provide limited hardware measurement data and cannot be used to investigate cell bit fails in functional SRAM arrays. This work presents a method for large-scale characterization of read stability and writeability in functional SRAM arrays using direct bit-line measurements. A test chip is implemented in a 45 nm CMOS process. Large-scale SRAM read/write metrics are measured and compared against conventional SRAM stability metrics. Results show excellent correlation to conventional SRAM read/write metrics as well as VMIN measurements near failure.
Keywords :
"Large-scale systems","Random access memory","Semiconductor device measurement","Stability","CMOS process","Cache memory","Testing","Failure analysis","Hardware","Switches"
Journal_Title :
IEEE Journal of Solid-State Circuits
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2009.2032698
Filename :
5308605
Link To Document :
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