Application of adaptive circuit partitioning algorithm to reduction of interconnections length between elements of VLSI circuit

This paper introduces a new adaptive partitioning algorithm (APA) for circuit partitioning, used for the reduction of the length of interconnections between elements of VLSI circuits. The main aim of this work is improvement of the partitioning quality obtained (described by the objective function f_c) and the reduction of the computational time (t) of the elaborated APA algorithm. These criteria result in decreasing the length of interconnections between elements of the designed integrated circuit and reducing the design time. The computations carried out for different ISCAS´89 circuit benchmarks showed that a proper choice of parameters considered during the partitioning can significantly improve the objective function f_c, while reducing the computational time t, which is very important in the design process of contemporary VLSI and GSI circuits.