Application of adaptive evolutionary algorithm for low power design of CMOS digital circuits

Author

Koziel, S. ; Szczesniak, W.

Author_Institution

Fac. of Electron., Telecommun., & Informatics, Tech. Univ. Gdansk, Poland

Volume

2

fYear

2002

fDate

2002

Firstpage

685

Abstract

This paper introduces a high-level synthesis method, based on an adaptive evolutionary algorithm, that utilizes an ´as soon as possible´ (ASAP) scheduling algorithm to reduce the switching power of CMOS circuits. Experimental verification of the algorithm has been performed for a set of test circuits chosen from ISCAS´85 and ISCAS´89 benchmarks, proving its efficiency. The obtained power consumption reduction varies for different benchmarks from 3 to 42 percent, without deteriorating the throughput of the whole system. Allowing deterioration of the throughput by 10 to 50 percent, the power reduction can be even larger (up to 52 percent).

Keywords

CMOS digital integrated circuits; circuit CAD; circuit optimisation; evolutionary computation; high level synthesis; integrated circuit design; integrated circuit modelling; integrated circuit testing; low-power electronics; AEA; ASAP algorithm efficiency; CMOS low power digital circuits; HLS; adaptive evolutionary design algorithms; as-soon-as-possible scheduling algorithms; benchmark test circuits; high-level synthesis methods; low power design; power consumption reduction; switching power reduction; system throughput; Algorithm design and analysis; Benchmark testing; CMOS digital integrated circuits; Circuit testing; Digital circuits; Evolutionary computation; High level synthesis; Scheduling algorithm; Switching circuits; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2002. 9th International Conference on

Print_ISBN

0-7803-7596-3

Type

conf

DOI

10.1109/ICECS.2002.1046261

Filename

1046261