Quick power supply noise estimation using hierarchically derived transfer functions

Author

Sugiyama, Satoshi ; Ikeda, Makoto ; Asada, Kunihiro

Author_Institution

Dept. of Electron. Eng., Univ. of Tokyo, Japan

Volume

2

fYear

2002

fDate

2002

Firstpage

713

Abstract

The analysis of power supply noise on VLSI chips is becoming important. In this paper we propose a new methodology for the estimation of power supply noise caused by digital switching activity. Using a transfer function calculated hierarchically from F-matrices, this method makes it possible with dramatically reduced computational cost to estimate power supply noise at all the nodes in power supply lines, which is linear to node number. The method is shown to be efficient and valid enough compared with HSPICE simulation.

Keywords

SPICE; VLSI; circuit simulation; integrated circuit modelling; integrated circuit noise; logic simulation; parameter estimation; power supply circuits; transfer function matrices; F-matrices; HSPICE simulation; VLSI chips; computational cost; digital switching activity; hierarchically derived transfer functions; node number; power supply line nodes; power supply noise estimation; Circuit noise; Circuit simulation; Computational efficiency; Noise reduction; Power supplies; Switches; Transfer functions; Upper bound; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2002. 9th International Conference on

Print_ISBN

0-7803-7596-3

Type

conf

DOI

10.1109/ICECS.2002.1046268

Filename

1046268