Computational kernel extraction for synthesis of power-managed sequential components

Low power has emerged as a principal theme in today´s electronics industry. We investigate the power reduction attaining optimization technique of functional partitioning at the register transfer level of design abstraction. The aim of the work is to develop an approach based on the concept of the computational kernel, a highly simplified logic block whose behavior mimics the behavior of the original specification. In this paper, we present a new method and tools for computational kernel extraction. We use a controller decomposition procedure, starting from its input probabilistic description. Preliminary experimental results show the effectiveness of our technique for low power design.