Title :
A polynomial time approximation scheme for rectilinear Steiner minimum tree construction in the presence of obstacles
Author :
Liu, Jian ; Zhao, Ying ; Shragowitz, Eugene ; Karypis, George
Author_Institution :
Dept. of Comput. Sci. & Eng., Minnesota Univ., Minneapolis, MN, USA
Abstract :
One problem in VLSI physical designs is to route multiterminal nets in the presence of obstacles. This paper presents a polynomial time approximation scheme for construction of a rectilinear Steiner minimum tree in the presence of obstacles. Given any m rectangular obstacles, n nodes and ε>0, the scheme finds a (1+ε)-approximation to the optimum solution in the time no(1ε)/, providing an alternative of previous heuristics. Note that m is assumed to be a constant; otherwise when we solve the sub-problem in a brute force manner, we cannot declare that it can be solved in constant time.
Keywords :
VLSI; circuit layout CAD; integrated circuit layout; network routing; network topology; polynomial approximation; trees (mathematics); VLSI physical designs; VLSI routing; heuristics; multiterminal nets; optimum solution approximation; polynomial time approximation scheme; rectangular obstacles; rectilinear Steiner minimum tree construction; Algorithm design and analysis; Costs; Dynamic programming; Optimized production technology; Polynomials; Routing; Steiner trees; Surface-mount technology;
Conference_Titel :
Electronics, Circuits and Systems, 2002. 9th International Conference on
Print_ISBN :
0-7803-7596-3
DOI :
10.1109/ICECS.2002.1046286