A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application

Author

Mu-Shan Lin ; Chien-Chun Tsai ; Chih-Hsien Chang ; Wen-Hung Huang ; Ying-Yu Hsu ; Shu-Chun Yang ; Chin-Ming Fu ; Mao-Hsuan Chou ; Tien-Chien Huang ; Ching-Fang Chen ; Tze-Chiang Huang ; Adham, Saman ; Min-Jer Wang ; Shen, William Wu ; Mehta, A.

Author_Institution

Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan

Volume

49

Issue

4

fYear

2014

fDate

Apr-14

Firstpage

1063

Lastpage

1074

Abstract

A 1 Tbit/s bandwidth PHY is demonstrated through CoWoS™ platform. Two chips: SOC and embedded DRAM (eDRAM), have been fabricated in TSMC 40 nm CMOS technology and stacked on a silicon interposer chip. 1024 DQ buses operating at 1.1 Gbit/s with VDDQ = 0.3 V are proven between SOC chip and eDRAM chip in experimental results with 1 mm signal trace length on the silicon interposer. A novel timing compensation mechanism is presented to achieve a low-power and small area eDRAM PHY that excludes PLL/DLL but retains good timing margin. Another data sampling alignment training approach is employed to enhance timing robustness. A compact low-swing IO also achieves power efficiency of 0.105 mW/Gbps.

Keywords

CMOS memory circuits; DRAM chips; compensation; elemental semiconductors; silicon; system-on-chip; timing; CoWoS Application; DQ buses; PLL/DLL-Less eDRAM PHY; SOC; Si; TSMC CMOS; bit rate 1.1 Gbit/s; data sampling alignment training approach; embedded DRAM; low-swing IO; power efficiency; signal trace length; silicon interposer chip; size 40 nm; timing compensation mechanism; timing robustness; voltage 0.3 V; Bandwidth; Clocks; Phase locked loops; Receivers; System-on-chip; Timing; Topology; 2.5D-IC; Chip on wafer on substrate; CoWoS; DLL; PHY; PLL; SII; eDRAM; low-swing IO; micro-bump; silicon-interposer; timing compensation;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2013.2297399

Filename

6774479