Monte Carlo Study of the Dynamic Performance of a 100-nm-Gate InAlAs/InGaAs Velocity Modulation Transistor

We report a Monte Carlo study of the dynamic behavior of an InAlAs/InGaAs velocity modulation transistor (VMT) based on the topology of a double-gate high electron mobility transistor (DG HEMT), which is a HEMT with two opposite gates controlling the carrier flow through the conducting channel. In the VMT, the source and drain electrodes are connected by two channels with different mobilities, and electrons are transferred between both by changing the gate voltages in differential mode (DM). As a result, the drain current is modulated while keeping the total carrier density constant, thus, in principle, avoiding capacitance charging/discharging delays. However, the low values taken by the transconductance, as well as the high capacitance between the two gates in DM operation, lead to a deficient dynamic performance.