A novel CMOS implementation of double-edge-triggered flip-flops

A CMOS implementation of a D-type double-edge-triggered flip-flop (DET-FF) is presented. A DET-FF changes its state at both the positive and the negative clock edge transitions. It has advantages with respect to both system speed and power dissipation. The design presented requires little overhead in circuit complexity. This CMOS D-type DET-FF is capable of operating at more than 50 MHz, which gives an equivalent system frequency of 100 MHz.