DocumentCode
385057
Title
Capacity planning of a photolithography work cell in a wafer manufacturing line
Author
Spence, Anne M. ; Welte, Douglas J.
Author_Institution
Stanford University, Stanford, CA
Volume
4
fYear
1987
fDate
31837
Firstpage
702
Lastpage
708
Abstract
This study was undertaken to help improve the performance of a semiconductor wafer fabrication line. We were concerned with understanding the capacity of the line, how to utilize limited resources to best improve manufacturing performance and to estimate the direction and magnitude of the improvements. The selected performance measure, the cycle time-throughput trade-off curve, aids decision makers to understand the relationship between average cycle time and throughput, enabling them to define the operational capacity of their system to complement the company´s manufacturing and marketing goals. With a detailed simulation model of a critical subsystem of a real fabrication line we explore the sensitivity of the trade-off curve to additional resources (operators and equipment), process improvements (reducing setup times and reducing rework) and operational rules (lot sizing and repairman wait time). The approach taken here and many of the qualitative insights gained are not restricted to the setting of a fabrication line and are applicable to many manufacturing environments.
Keywords
Capacity planning; Fabrication; Lithography; Lot sizing; Manufacturing; Production; Research and development; Semiconductor device manufacture; Throughput; Time measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Robotics and Automation. Proceedings. 1987 IEEE International Conference on
Type
conf
DOI
10.1109/ROBOT.1987.1087949
Filename
1087949
Link To Document