• DocumentCode
    3851112
  • Title

    A 2 Gb/s 5.6 mW Digital LOS/NLOS Equalizer for the 60 GHz Band

  • Author

    Ji-Hoon Park;Brian Richards;Borivoje Nikolic

  • Author_Institution
    Electrical Engineering and Computer Sciences, Berkeley Wireless Research Center, University of California, Berkeley, Berkeley, CA, USA
  • Volume
    46
  • Issue
    11
  • fYear
    2011
  • Firstpage
    2524
  • Lastpage
    2534
  • Abstract
    The wide unlicensed bandwidth of a 60 GHz channel presents an attractive opportunity for high data rate and low power personal area networks (PANs). The use of single-carrier modulation can yield energy-efficient transmitter and receiver implementation, but equalization of the long channel response in non-line-of-sight (NLOS) conditions presents a significant challenge. A digital equalizer for 60 GHz channels has been designed for both line of sight (LOS) and NLOS channel conditions to meet the IEEE WPAN standard. Power consumption is minimized by using a parallelized distributed arithmetic (DA) architecture. A 2 mm × 2 mm test chip in 65nm CMOS implements a 6 tap feedforward and 32 tap feedback equalizer that can be configured to cancel the response of up to 72 symbols, and consumes 5.6 mW at 2 Gb/s throughput. The chip also includes a channel estimator based on a Golay correlator for setting the equalizer coefficients and estimating frequency and timing error.
  • Keywords
    "Table lookup","Decision feedback equalizers","Channel estimation","Power demand","Receivers","OFDM"
  • Journal_Title
    IEEE Journal of Solid-State Circuits
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.2011.2164137
  • Filename
    6015501