Highly scalable IP core to accelerate the forward/backward modified discrete cosine transform in MP3 implemented to FPGA and low-power ASIC

Modified discrete cosine transform (MDCT) is used in many audio coding standards for time-to-frequency transformation of digital signals. It is one of the most computationally intensive operations in audio compression and decompression processes. In this study, optimised dedicated hardware architectures utilised in a highly scalable MDCT IP core are proposed to accelerate the forward/backward MDCT computation in MP3 audio coding standard. The MDCT IP core is pipelined, capable to compute both the forward and backward MDCT on the same hardware and it is optimised with field-programmable gate arrays (FPGA) and application-specific integrated circuit (ASIC) technologies. The MDCT IP core is implemented to FPGA and ASIC, whereby the FPGA implementation used Xilinx Virtex-4 FPGA, while the ASIC implementation used AMS 350 nm CMOS standard cell library. The MDCT IP core is further optimised and implemented utilising UMC 90 nm CMOS low-power digital libraries and clock gating technique. As a result, power consumption and the area are reduced significantly. The proposed hardware architectures are optimised to achieve high computational speed with high precision, and therefore they are suitable for a lossless audio compression. In particular, high computational speed permits multichannel real-time acceleration of the forward and backward MDCT computation.