Title :
Three-Level Cell Topology for a Multilevel Power Supply to Achieve High Efficiency Envelope Amplifier
Author :
Daniel Diaz;Miroslav Vasic;Óscar Garcia;Jesús A. Oliver;Pedro Alou;Roberto Prieto;José A. Cobos
Author_Institution :
Centre of Electronics, Industry of the Universidad Polit?cnica de Madrid, Madrid, Spain
Abstract :
This paper presents an envelope amplifier solution for envelope elimination and restoration (EER), that consists of a series combination of a switch-mode power supply (SMPS), based on three-level voltage cells and a linear regulator. This cell topology offers several advantages over a previously presented envelope amplifier based on a different multilevel topology (two-level voltage cells). The topology of the multilevel converter affects to the whole design of the envelope amplifier and a comparison between both design alternatives regarding the size, complexity and the efficiency of the solution is done. Both envelope amplifier solutions have a bandwidth of 2 MHz with an instantaneous maximum power of 50 W. It is also analyzed the linearity of the three-level cell solution, with critical importance in the EER technique implementation. Additionally, considerations to optimize the design of the envelope amplifier and experimental comparison between both cell topologies are included.
Keywords :
"Computer architecture","Microprocessors","Topology","Regulators","Bandwidth","Voltage control","Optimization"
Journal_Title :
IEEE Transactions on Circuits and Systems I: Regular Papers
DOI :
10.1109/TCSI.2012.2185307