Abstract :
Tunnel FETs (TFETs) are being intensively investigated for their potential in achieving subthermal switching slopes and extremely low leakage currents. Recently, a promising concept has been proposed: the electron-hole bilayer TFET (EHBTFET), which exploits carrier tunneling through a bias-induced electron-hole bilayer. In this paper, we show that, through appropriate optimization of the Ge EHBTFET, it is possible to achieve superior static characteristics at low supply voltages, when compared with a double-gate Ge MOSFET with similar geometry. The EHBTFET provides an improved average subthreshold slope (from 0 to |VDD| = 0.25 V) of 30 mV/dec against 60 mV/dec at same |ION| ~ 0.18 μA/μm, doubled inverter gain, and larger noise margins, suggesting great potential for low-power applications. The dynamic behavior of the devices is investigated by transient simulations of simple circuits based on complementary inverters. Due to the increased total EHBTFET capacitance, the fanout-of-1 delay is larger than that in MOSFET, with 11 ns versus 4 ns at |VDD| = 0.25 V. However, the EHBTFET results to be more robust than MOSFET for voltage scaling, as the leakage component is far from approaching the dynamic component of the total switching energy at low VDD.
Keywords :
"MOSFET circuits","Logic gates","Inverters","Tunneling","Capacitance","Transistors"
