DocumentCode
385649
Title
A system-level solution to domino synthesis with 2 GHz application
Author
Chappell, B. ; Wang, X. ; Patra, P. ; Saxena, P. ; Vendrell, J. ; Gupta, S. ; Varadarajan, S. ; Gomes, W. ; Hussain, S. ; Krishnamurthy, H. ; Venkateshmurthy, M. ; Jain, S.
Author_Institution
Intel Corp., USA
fYear
2002
fDate
2002
Firstpage
164
Lastpage
171
Abstract
System structure and a taped out 0.18u 2 GHz product application result are described for a domino synthesis capability that covers all aspects of domino design, from estimation to silicon-ready layout, with custom-class optimization. The described optimization flow, abstraction modes, and key cost factors deliver power-optimized, noise-correct domino performance on complex logic.
Keywords
circuit optimisation; logic CAD; 2 GHz; abstraction modes; complex logic; cost factors; custom-class optimization; domino design; domino synthesis; estimation; optimization flow; power-optimized noise-correct domino performance; silicon-ready layout; system structure; taped out product application; CMOS logic circuits; Circuit noise; Circuit synthesis; Cost function; Delay; Design optimization; Logic circuits; Logic design; Logic functions; Microprocessors;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 IEEE International Conference on
ISSN
1063-6404
Print_ISBN
0-7695-1700-5
Type
conf
DOI
10.1109/ICCD.2002.1106765
Filename
1106765
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