Title :
A test processor concept for systems-on-a-chip
Author :
Galke, C. ; Pflanz, M. ; Vierhaus, H.T.
Author_Institution :
Comput. Eng. Dept., Brandenburg Univ. of Technol. Cottbus, Germany
Abstract :
This paper introduces a new concept for the self test of systems on a chip (SoCs) with embedded processors. We propose hardware- and software-based test strategy. A minimum sized test processor was designed in order to perform on-chip test functions. Its architecture contains special adopted registers to realize LFSR or MISR functions for pattern de-compaction and pattern filtering. High-performance interfaces allow parallel and serial pattern in and output, and a fast test vector comparison. The architecture is scalable and is based on a standard RISC architecture in order to facilitate the use of standard compilers.
Keywords :
automatic testing; computer testing; hardware-software codesign; logic testing; system-on-chip; LFSR; MISR; RISC architecture; embedded processors; on-chip test functions; pattern de-compaction; pattern filtering; self test; systems on a chip; test strategy; Automatic testing; Birth disorders; Compaction; Filtering; Logic devices; Logic testing; Process design; Reduced instruction set computing; System testing; System-on-a-chip;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 IEEE International Conference on
Print_ISBN :
0-7695-1700-5
DOI :
10.1109/ICCD.2002.1106772
