DocumentCode
385822
Title
Parasitic capacitance modeling for multilevel interconnects
Author
Tani, Sadahiro ; Uchida, Yoshihiro ; Furuie, Makoto ; Tsukiyama, Shuji ; Lee, Buyeol ; Nishi, Shuji ; Kubota, Yasushi ; Shirakawa, Isao ; Imai, Shigeki
Author_Institution
Graduate Sch. of Eng., Osaka Univ., Japan
Volume
1
fYear
2002
fDate
2002
Firstpage
59
Abstract
The problem of calculating parasitic capacitance between interconnects is investigated with the main theme focused on deriving approximate expressions for calculating parasitic capacitance between two crossing interconnects. The interconnects are divided into a few basic coupling regions, in such a way that the capacitance in a region can be represented by a simple expression adjusted to the results computed by an electromagnetic field solver based on a two-dimensional capacitance model. An approximate expression of the total capacitance between two crossing interconnects is obtained by summing the capacitances in all regions. In order to evaluate the accuracy of this approximation, the capacitance calculated by the attained expression is compared with the one obtained by a three-dimensional field solver, and it turns out that the error is less than 5%.
Keywords
capacitance; electromagnetic coupling; electromagnetic field theory; error analysis; integrated circuit interconnections; integrated circuit metallisation; integrated circuit modelling; 2D capacitance model; 3D field solver; approximation error; crossing interconnects; electromagnetic field solver; interconnect coupling regions; multilevel interconnects; parasitic capacitance modeling; total capacitance; Acceleration; Capacitors; Clocks; Conductors; Information science; Integrated circuit interconnections; Large scale integration; Manufacturing processes; Packaging; Parasitic capacitance;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on
Print_ISBN
0-7803-7690-0
Type
conf
DOI
10.1109/APCCAS.2002.1114908
Filename
1114908
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