A high-level synthesis method for simultaneous placement and scheduling considering data communication delay

With the development of deep submicron technology, wire delay on an LSI chip is becoming relatively larger than gate delay. In the conventional VLSI design flow, high-level design is usually performed without information about the physical layout design. The estimation of wire delay during the high-level design is not accurate and the final performance, after the physical layout design, might not satisfy requirements. In order to overcome this problem, wire delay determined by placement and routing must be considered even in high-level design. In this paper we propose a method to achieve high speed processing for a given processing algorithm by performing scheduling and placement of operations simultaneously. With this method, wire delay based on the placement is precisely considered and may be minimized during the scheduling of operations.