• DocumentCode
    385851
  • Title

    A hierarchical standard cell placement method based on a new cluster placement model

  • Author

    Wakabayashi, Shin Ichi ; IWAUCHI, Nobuyuki ; Kubota, Hajime

  • Author_Institution
    Graduate Sch. of Eng., Hiroshima Univ., Japan
  • Volume
    1
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    273
  • Abstract
    In this paper, we propose a new hierarchical timing-driven standard-cell placement method, in which a new cluster placement model is introduced. The proposed method is divided into three phases: clustering cells, global placement and detailed placement. After clustering cells, in the global placement phase, we determine and improve cluster placement by a simulated annealing based method. In most previous methods, the shape of any cluster was restricted to a square. In the proposed method, however, we remove this restriction, and propose a new placement model, called the Amoeba model, in which the shape of a cluster can be a collection of connected squares. Since the flexibility of cluster placement is increased by the Amoeba model, we can obtain a high quality placement satisfying timing constraints. In the detailed placement phase, we assign cells to cell rows under the non-overlapping constraint of cells with a constructive approach. Experimental results show the effectiveness of the proposed method with the new cluster placement model.
  • Keywords
    circuit layout CAD; circuit optimisation; delays; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; simulated annealing; timing; Amoeba model; cell assignment; cell clustering; cell rows; cluster placement model; cluster shape; detailed placement phase; global placement; hierarchical standard cell placement method; nonoverlapping cell constraint; placement flexibility; simulated annealing based method; timing constraints; timing-driven standard-cell placement; Circuit simulation; Clustering algorithms; Clustering methods; Computational modeling; Law; Phase estimation; Shape; Simulated annealing; Timing; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on
  • Print_ISBN
    0-7803-7690-0
  • Type

    conf

  • DOI
    10.1109/APCCAS.2002.1114952
  • Filename
    1114952