Implementing a reconfigurable MAP decoder on a soft core processor system

Author

Dimyati, K. ; Ismai, M.F.

Author_Institution

Dept. of Electr. Eng., Malaya Univ., Kuala Lumpur, Malaysia

Volume

1

fYear

2002

fDate

2002

Firstpage

285

Abstract

This paper presents a hardware implementation of a Maximum a Posteriori (MAP) decoder system on a soft core processor system which is embedded on an FPGA. The MAP decoder system is developed to perform error correction operations in a wireless baseband transmission through an additive white Gaussian noise (AWGN) channel. The implementation of the decoding algorithm in the soft-core processor system is described. The expected error correction capability with several reconfigurable parameters is shown.

Keywords

AWGN channels; decoding; digital radio; digital signal processing chips; error correction; field programmable gate arrays; performance evaluation; telecommunication computing; turbo codes; AWGN channel; DSP; FPGA; additive white Gaussian noise; decoding algorithm; error correction operations; reconfigurable MAP decoder; reconfigurable parameters; soft core processor system; turbo decoder; wireless baseband transmission; AWGN; Abstracts; Additive white noise; Decoding; Error correction; Field programmable gate arrays; Gaussian noise; Hardware; Signal to noise ratio; Turbo codes;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on

Print_ISBN

0-7803-7690-0

Type

conf

DOI

10.1109/APCCAS.2002.1114954

Filename

1114954