DocumentCode
385868
Title
Low-complexity systolic multiplier over GF(2m) using weakly dual basis
Author
Lee, Chiou-Yng ; Lu, Ya-Cheng ; Lu, Erl-Huei
Author_Institution
Chunghwa Telecom. Lab., Taiwan
Volume
1
fYear
2002
fDate
2002
Firstpage
367
Abstract
This paper offers a new bit-parallel systolic multiplier for GF(2m) using the weakly dual basis. The multiplier is composed of two units $multiplication and transformation. The structure of the multiplication unit includes m2 cells, each cell is composed of one 2-input AND gate, one 2-input XOR gate and three/four 1-bit latches. The structure of the transformation unit is established by the 2-input XOR-tree. The latency of the multiplier only requires m+[log2m] clock cycles.
Keywords
digital arithmetic; flip-flops; logic design; logic gates; systolic arrays; transforms; GF(2m) low-complexity bit-parallel systolic multipliers; dual-input AND gates; dual-input XOR gates; dual-input XOR-trees; finite field arithmetic operations; multiplication unit structure cells; multiplier latency clock cycle requirements; single-bit latches; transformation units; weakly dual basis; Arithmetic; Circuits; Clocks; Computer architecture; Concurrent computing; Cryptography; Delay; Error correction codes; Galois fields; Polynomials;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on
Print_ISBN
0-7803-7690-0
Type
conf
DOI
10.1109/APCCAS.2002.1114972
Filename
1114972
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