A fully digital feedback equalizer for MDFE read channel

Author

Yong, S.F. ; Xu, Y.P. ; Bi, L.

Author_Institution

Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore

Volume

1

fYear

2002

fDate

2002

Firstpage

373

Abstract

The design of a feedback equalizer (FE) in multi-level decision feedback equalization (MDFE) for magnetic recording channels is presented. The fully digital feedback equalizer is implemented with a look-up-table based architecture. The FE has 11 taps where the past decisions are stored and subsequently used to determine the feedback coefficients. With the insertion of a single pipeline, two clock periods are allowed for the completion of the critical timing loop. The improvement in throughput is made possible with the application of look-ahead computation. Based on a 0.35 μm CMOS technology, the post-layout simulation results show that the FE is capable of operating at a clock rate of 132 MHz under typical conditions.

Keywords

CMOS logic circuits; circuit CAD; circuit simulation; decision feedback equalisers; integrated circuit design; integrated circuit modelling; logic CAD; logic simulation; magnetic recording; magnetic storage; pipeline arithmetic; table lookup; timing; 0.35 micron; 132 MHz; CMOS technology; FE past decision storage taps; LUT; MDFE; clock rate; critical timing loop clock periods; feedback coefficients; fully digital feedback equalizers; look-ahead computation; look-up-table based architecture; magnetic recording channels; multi-level DFE magnetic read channels; multi-level decision feedback equalization; pipeline architecture; CMOS technology; Clocks; Computational modeling; Computer applications; Decision feedback equalizers; Iron; Magnetic recording; Pipelines; Throughput; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on

Print_ISBN

0-7803-7690-0

Type

conf

DOI

10.1109/APCCAS.2002.1114973

Filename

1114973