DocumentCode
385887
Title
High density bit-serial FPGA with LUT embedding shift register function
Author
Isshiki, T. ; Ohta, A. ; Watanabe, T. ; Nakada, T. ; Akahane, K. ; Sisla, I. ; Li, D. ; Kunieda, H.
Author_Institution
VLSI Design & Educ. Center, Univ. of Tokyo, Japan
Volume
1
fYear
2002
fDate
2002
Firstpage
475
Abstract
A new FPGA architecture and its VLSI implementation for bit-serial circuits are described. Its LUT (lookup table) is equipped with a shift register function that can efficiently implement bit-serial circuits. Comparisons against Xilinx XC4000XL FPGAs shows the effectiveness of this new FPGA architecture on bit-serial circuits.
Keywords
CMOS logic circuits; VLSI; field programmable gate arrays; floating point arithmetic; integrated circuit design; logic design; shift registers; table lookup; CMOS high density bit-serial FPGA; CMOS process; FPGA architecture; LUT-embedded shift register functions; VLSI; bit-serial circuits; floating-point arithmetic; logic block routing; logic core elements; lookup tables; Computer architecture; Field programmable gate arrays; Large-scale systems; Logic circuits; Logic devices; Programmable logic devices; Routing; Shift registers; Switches; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on
Print_ISBN
0-7803-7690-0
Type
conf
DOI
10.1109/APCCAS.2002.1115034
Filename
1115034
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