DocumentCode
385894
Title
An efficient architecture for adaptive progressive thresholding
Author
Tian, H. ; Lam, S.K. ; Srikanthan, T. ; Chang, C.H.
Author_Institution
Center for High Performance Embedded Syst., Nanyang Technol. Univ., Singapore
Volume
1
fYear
2002
fDate
2002
Firstpage
513
Abstract
A new pipelined architecture for adaptive progressive thresholding (APT) is proposed. Unlike the conventional architectures that rely heavily on multipliers and dividers to evaluate the maximum between-class variance, our method employs a reconfigurable logarithmic computing unit to simplify the circuitry and increases the application´s ability to handle operational variation. Our logarithmic conversion algorithm avoids large look-up tables by streaming the operand´s bits into segments so that several small look-up tables and simple adders and shifters are sufficient to guarantee an accurate result. Besides being cost effective, the proposed architecture has also significantly reduced the latency of the critical pipelined stage.
Keywords
adaptive signal processing; adders; image processing equipment; image segmentation; pipeline processing; reconfigurable architectures; shift registers; table lookup; APT; adaptive progressive thresholding architecture; adders; cost effectiveness; digital image segmentation; logarithmic conversion algorithm; look-up table size; maximum between-class variance; operand bit-streamed segments; operational variation handling; pipelined architecture; pipelined stage latency; reconfigurable logarithmic computing unit; shifters; Adders; Arithmetic; Circuits; Computer architecture; Costs; Delay; Embedded system; Image segmentation; Pixel; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on
Print_ISBN
0-7803-7690-0
Type
conf
DOI
10.1109/APCCAS.2002.1115051
Filename
1115051
Link To Document