Title :
Real-time deblocking filter for MPEG-4 systems
Author :
Fang, Hung-Chi ; Wang, Fi-Chih ; Chen, Liang-Gee
Author_Institution :
Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
This paper presents a deblocking filter architecture in the MPEG-4 standard. This architecture performs as a 1D nonlinear filter across the block boundary to efficiently suppress blocking artifacts. Two shift register banks are used in the design; their use greatly reduces the control complexity of data flow. Due to efficient scheduling, the size of storage and the total clock cycles are minimized. The maximum processing rate of this architecture mapped in 0.35 μm technology is 30 Mpixels/sec, which can support NTSC resolution at 30 frames per second. The power consumption of the design is 46.6 mW while operating frequency is 81 MHz.
Keywords :
adaptive filters; discrete cosine transforms; image resolution; image sequences; nonlinear filters; nonlinear network synthesis; video coding; 0.35 micron; 1D nonlinear filter; 46.6 mW; 81 MHz; DCT-based video coding standards; MPEG-4 standard; MPEG-4 systems; NTSC resolution; architecture maximum processing rate; block boundary; blocking artifacts suppression; data flow control complexity; operating frequency; power consumption; real-time deblocking filter architecture; scheduling; shift register banks; storage minimization; technology mapping; total clock cycles minimization; Design engineering; Digital signal processing; Discrete cosine transforms; Filtering; Iterative algorithms; Low pass filters; MPEG 4 Standard; Quadratic programming; Quantization; Real time systems;
Conference_Titel :
Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on
Print_ISBN :
0-7803-7690-0
DOI :
10.1109/APCCAS.2002.1115058
