Area efficient current steering DAC using current tuning

Author

Rafeeque, K. P Sunil

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol. Madras, Chennai, India

Volume

1

fYear

2002

fDate

2002

Firstpage

559

Abstract

A 10 bit segmented (5+5 bit) high speed current steering DAC is presented in this paper. Devices with small area are used to reduce the total area without affecting linearity. A current tuning loop is suggested to overcome the sizing mismatch error. The master slave concept is used along with this to generate multiple copies of weighted current sources. Sizing reduces the area requirement to 20% of the 2ⁿ unit cell design. The tuning reduces the DNL and INL to 0.1 LSB without considering any random error.

Keywords

CMOS integrated circuits; circuit CAD; circuit simulation; circuit tuning; current-mode circuits; digital-analogue conversion; errors; integrated circuit design; integrated circuit modelling; 10 bit; CMOS current steering DAC; D/A converters; DNL/INL reduction; area efficient DAC design; current tuning; current tuning loops; device area requirements; device linearity; master slave concept; random errors; segmented high speed DAC; sizing mismatch errors; unit cell design; weighted current source multiple copy generation; Analog circuits; Calibration; Clocks; Decoding; Frequency conversion; Linearity; Master-slave; Signal resolution; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on

Print_ISBN

0-7803-7690-0

Type

conf

DOI

10.1109/APCCAS.2002.1115066

Filename

1115066