DocumentCode
3860975
Title
A new expression for breakdown voltage of practical linearly graded p-n junction
Author
A.P. Silard;M.J. Duta
Author_Institution
Dept. of Electron., Polytech Inst., Bucharest, Romania
Volume
38
Issue
2
fYear
1991
Firstpage
422
Lastpage
424
Abstract
An analytical investigation of realistic linearly graded silicon p-n junctions, currently used in high-voltage device structures, is performed. Basic corrections to the fundamental theory of reverse-biased, linearly graded p-n junctions are analytically formulated. Closed-form relations for the breakdown voltage BV and peak space-charge region extension (at breakdown) in practical linearly graded junctions are presented. A thorough investigation of linearly graded junctions used in power devices is performed. Basic corrections to the fundamental theory of linearly graded junctions have been analytically formulated. It is shown that the departure from the classical linearly graded case is more obvious as the background impurity concentration drops below C/sub B/=10/sup 15/ cm/sup -3/ and the impurity gradient a increases above 5*10/sup 16/ cm/sup -4/. For C/sub B/10/sup 16/ cm/sup -4/, the linearly graded junction behaves like an abrupt one. For a>10/sup 19/ cm/sup -4/ and C/sub B/<10/sup 16/ cm/sup -3/, the linearly graded case is reduced to the abrupt one.
Keywords
"P-n junctions","Linear approximation","Impurities","Silicon devices","Performance analysis","Breakdown voltage","Computer peripherals","Production facilities","Thyristors","Aluminum"
Journal_Title
IEEE Transactions on Electron Devices
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.69927
Filename
69927
Link To Document