Title :
Tuning logic simulators for timing analysis
Author :
D.M. Maksimovic;V.B. Litovski
Author_Institution :
Fac. of Electron. Eng., Nis Univ., Serbia
fDate :
5/13/1999 12:00:00 AM
Abstract :
An original method for digital circuit delay estimation within a logic simulator framework and HDL modelling mechanism needed for its implementation are proposed. The method is implemented using the simulator Alecsis and its efficiency is demonstrated on a set of ISCAS´85 benchmark circuits.
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19990545
