Efficient architectures for time-interleaved oversampling delta-sigma converters

A design methodology utilizing the concept of time-interleaved oversampling delta-sigma conversion is developed and explored to obtain efficient hardware architectures. In this approach, the time-domain internal node expressions of a standard modulator are rearranged according to the desired channel count to produce a modular structure with reduced hardware requirements. It is shown that the proposed approach results in an architecture which is functionally equivalent to that of the conventional method based on the block-digital filtering concept, but with a reduced hardware complexity. The theoretical results are also verified by means of behavioral simulations.