Evaluation of two-summand adders implemented in ECDL CMOS differential logic

Four different adders were implemented using a CMOS differential logic, enable/disable differential CMOS logic (ECDL). The authors discuss the design and implementation of several common addition algorithms using ECDL. These adders have the self-timed characteristic. Comparisons are made among these algorithms in terms of delay and area. The actual implementation was done with MOSIS 3- mu m scalable process. Evaluations are performed in terms of area and delay. One conclusion that can be made is that the carry-skip adder seems to have the best speed/area combined performance. A first-order modeling method is used to estimate the area and speed of different implementations.