DocumentCode :
3862020
Title :
A pipelined noise shaping coder for fractional-N frequency synthesis
Author :
M. Kozak;I. Kale
Author_Institution :
Nokia Res. Center, Farnborough, UK
Volume :
50
Issue :
5
fYear :
2001
Firstpage :
1154
Lastpage :
1161
Abstract :
In this paper, we present the design considerations and implementation aspects of a pipelined all-digital fourth-order multi-stage-noise-shaping (MASH) delta-sigma (/spl utri//spl Sigma/) modulator suitable for fractional-N (F-N) phase-locked loop (PLL) frequency synthesis applications. In an effort to reduce the hardware complexity and power consumption, the alignment registers, which are normally required in pipelined adders, are eliminated by taking advantage of static modulator input. The MASH modulator has successfully been targeted to an Altera/sup TM/ field-programmable-gate-array (FPGA) device. The functional operation of the modulator has been verified through structural bit-level simulations as well as experimental results on the actual FPGA implementation.
Keywords :
"Noise shaping","Multi-stage noise shaping","Phase locked loops","Field programmable gate arrays","Phase modulation","Delta modulation","Frequency locked loops","Frequency synthesizers","Hardware","Energy consumption"
Journal_Title :
IEEE Transactions on Instrumentation and Measurement
Publisher :
ieee
ISSN :
0018-9456
Type :
jour
DOI :
10.1109/19.963176
Filename :
963176
Link To Document :
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