DocumentCode
3862334
Title
Energy-Efficient Optimization of the Viterbi ACS Unit Architecture
Author
Hoang Q. Dao;Bart R. Zeydel;Vojin G. Oklobdzija
Author_Institution
Advanced Computer Systems Engineering Laboratory, Department of Electrical and Computer Engineering, University of California, Davis, CA 95616. hqdao@acsel-lab.com
fYear
2005
Firstpage
233
Lastpage
236
Abstract
Different architectural approaches for saving energy are considered for the ACS unit of a Viterbi decoder. It was found that although providing less throughput improvement than parallelism, pipelining is more energy efficient. The optimal mix of these two architectures favors more pipelining at lower throughput requirements
Keywords
"Energy efficiency","Viterbi algorithm","Circuits","Decoding","Throughput","Parallel processing","Pipeline processing","Computer architecture","Energy consumption","Multiplexing"
Publisher
ieee
Conference_Titel
Asian Solid-State Circuits Conference, 2005
Print_ISBN
0-7803-9162-4
Type
conf
DOI
10.1109/ASSCC.2005.251708
Filename
4017574
Link To Document