Title :
A 1.1-Gb/s 4092-bit Low-Density Parity-Check Decoder
Author :
Engling Yeo;Borivoje Nikolic
Author_Institution :
Read Channel Architecture, STMicroelectronics, San Diego, CA, USA
Abstract :
A 4092-bit low-density parity-check decoder, based on staggered decoding schedule, is implemented in a 130nm 6M CMOS technology. The rate 0.75 code is based on finite-field geometries. Serial, shift-register based architecture enables a compact decoder implementation. The chip has a 4.0mm2 core and operates at 1.1 GHz with 1.2V supply, resulting in a throughput of 1.1Gb/s per iteration
Keywords :
"Parity check codes","Throughput","Iterative decoding","CMOS technology","Geometry","Computer architecture","Iterative algorithms","Arithmetic","Galois fields","Wireless communication"
Conference_Titel :
Asian Solid-State Circuits Conference, 2005
Print_ISBN :
0-7803-9162-4
DOI :
10.1109/ASSCC.2005.251709
