DocumentCode :
3862542
Title :
Accelerating Microblaze Floating Point Operations
Author :
Jiri Kadlec;Roman Bartosinski;Martin Danek
Author_Institution :
Department of Signal Processing, ?TIA AV ?R, v.v.i., Pod Vod?renskou v?? 4, Prague, CZ. email: kadlec@utia.cas.cz
fYear :
2007
Firstpage :
621
Lastpage :
624
Abstract :
The MicroBlaze processor serves in many FPGA designs as the central 32 bit CPU with access to the global off chip memory and peripherals. MicroBlaze provides FSL links for up to 8 coprocessors. We present two MicroBlaze designs. The first design works with 8 PicoBlaze-based accelerators for pipelined, single-precision floating point vector-oriented operations, and delivers over 1.2 GFLOPs. The second design uses 4 similar double precision accelerators and delivers 600 MFLOPs. The acceleration results are documented on batch computation of a finite impulse response filter. Each PicoBlaze soft core can be re-programmed by MicroBlaze. This provides a framework for a partial dynamic change of the functionality of accelerators. This program change can be done via the FSL link in parallel with the current computation of the accelerator.
Keywords :
"Acceleration","Hardware","Registers","Field programmable gate arrays","Coprocessors","Delay","Clocks","Signal processing","Chromium","Finite impulse response filter"
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on
ISSN :
1946-147X
Print_ISBN :
978-1-4244-1059-0
Electronic_ISBN :
1946-1488
Type :
conf
DOI :
10.1109/FPL.2007.4380731
Filename :
4380731
Link To Document :
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