On Optimization of Miller-Rabin Primality Test on TI TMS320C54x Signal Processors

In this paper, possibilities of realization of Miller-Rabin big number primality test on assembler of Texas Instruments digital signal processors of TMS320C54x family are considered. The importance of realization of the reliable Miller-Rabin primality test of very large numbers for the purpose of asymmetric RSA cryptographic algorithm is emphasized. An experimental analysis of the efficiency of Miller-Rabin test realization on appropriate signal processors of TMS320C54x family are presented. Possible optimization techniques for Miller-Rabin algorithm related to multiplication and modular reduction are evaluated. We modify the Karatsuba-Offman´s algorithm and obtain a less recursive algorithm and applied it for the purpose of multiplication in the Miller-Rabin test. Obtained results justify the use of the application of coprocessor module on the basis on the considered signal processors with a hardware random number generator and the Miller-Rabin´s algorithm for primality testing. Applying these modules, it could be achieved considerably higher level of the system security regarding to the software-only security systems.