Title :
Implementation of the ALICE Trigger System
Author :
A. Bhasin;D. Evans;G.T. Jones;P. Jovanovic;A. Jusko;L. Kralik;M. Krivda;C. Lazzeroni;R. Lietava;L. Sandor;J. Urban;O. Villalobos Baillie
Author_Institution :
School of Physics and Astronomy, The University of Birmingham, Birmingham, UK
fDate :
4/7/2016 12:00:00 AM
Abstract :
The ALICE trigger system consists of the Central Trigger Processor (CTP) and 24 Local Trigger Units (LTU) that act as a uniform interface to sub-detector front-end electronics. The CTP generates three levels of hierarchical hardware triggers - L0, L1 and L2. At any time, the 24 sub-detectors of the ALICE experiment are dynamically partitioned into up to 6 independent clusters. Trigger selection includes the past-future protection a fully programmable hardware mechanism of controlling the event pile-up. The system contains a number of options that enhance the testability: the SnapShot memories both emulate logic inputs and monitor the logic operation - they enable on-line and in situ detection of system malfunction; more than 1200 signal counters, with simple on-line access, monitor the system performance and check the consistency; the ScopeProbe option enables a direct oscilloscope access to the system inputs, outputs and relevant internal signals. Some of the "common" CTP functions - down-scaling of trigger classes, synchronization of trigger inputs, etc. - have been realized in a way that is economical on logic resources and offers performance benefits. The implementation of those options using the FPGAs is the main topic of the presentation.
Keywords :
"Logic testing","Hardware","Protection","Data acquisition","Physics","System testing","Monitoring","Large Hadron Collider","Timing","Astronomy"
Conference_Titel :
Real-Time Conference, 2007 15th IEEE-NPSS
Print_ISBN :
978-1-4244-0866-5
DOI :
10.1109/RTC.2007.4382861