CMP process optimization on temporary-bonded wafer for via-last through-silicon-via from backside

Chemical Mechanical Polishing (CMP) on thinned bonded wafer is one of the key challenges in the entire via-last TSV process flow. This paper addresses the issue of oxide loss and barrier metal residue during CMP process. The impact of pre-CMP thermal budget on (i) CMP polishing rate, (ii) uniformity and (iii) selectivity to the underlying dielectric on bonded wafers is investigated. We further looked into other factors including incoming wafer warpage, total thickness variation (TTV) of the adhesive layer, Cu anneal process and dielectric deposition. In this paper, we propose an enhanced CMP-based via-last process flow based on the study of Cu annealing process and adhesive thickness.