DocumentCode
386666
Title
Compression and technology mapping of logic circuits
Author
Correia, Vinícius Pazutti ; Reis, André Inácio
fYear
2002
fDate
2002
Firstpage
283
Lastpage
286
Abstract
This paper presents a new approach to technology mapping. The matching phase is done across several subject trees by identifying functional equivalencies. This affects the cost of mapping a given node by dividing the implementation cost among several subject trees. The covering phase is done by considering the cost of sharing logic among several trees. Some preliminary results are shown for the compression by equivalence checking part of the algorithm.
Keywords
binary decision diagrams; circuit simulation; decision trees; equivalence classes; integrated circuit design; logic CAD; logic simulation; BDD structures; circuit tree representation; covering phase; equivalence checking compression algorithm; functional equivalence identification; implementation cost; logic circuit technology mapping/compression; node mapping cost; subject tree matching phase; tree shared logic; Cost function; Integrated circuit technology; Libraries; Logic circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuits and Systems Design, 2002. Proceedings. 15th Symposium on
Print_ISBN
0-7695-1807-9
Type
conf
DOI
10.1109/SBCCI.2002.1137672
Filename
1137672
Link To Document