• DocumentCode
    387049
  • Title

    A 25ns 16K CMOS PROM using a 4-transistor cell

  • Author

    Pathak, S. ; Kupec, J. ; Murphy, C. ; Sawtelle, D. ; Shrivastava, R. ; Jenne, F.

  • Author_Institution
    Cypress Semiconductor Corp., San Jose, CA, USA
  • Volume
    XXVIII
  • fYear
    1985
  • fDate
    13-15 Feb. 1985
  • Firstpage
    162
  • Lastpage
    163
  • Abstract
    A 25ns, 250mW, 2K×8 PROM using 1.2μ N-well CMOS technology will be described. Speed and programmability have been optimized by separating read and write transistors in a 4-transistor differential cell. A substrate bias generator raises the latchup immunity to over 200mA.
  • Keywords
    CMOS logic circuits; Delay effects; Electrons; Logic programming; Monitoring; PROM; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1985.1156754
  • Filename
    1156754
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=387049