Title :
A 25ns 16K CMOS PROM using a 4-transistor cell
Author :
Pathak, S. ; Kupec, J. ; Murphy, C. ; Sawtelle, D. ; Shrivastava, R. ; Jenne, F.
Author_Institution :
Cypress Semiconductor Corp., San Jose, CA, USA
Abstract :
A 25ns, 250mW, 2K×8 PROM using 1.2μ N-well CMOS technology will be described. Speed and programmability have been optimized by separating read and write transistors in a 4-transistor differential cell. A substrate bias generator raises the latchup immunity to over 200mA.
Keywords :
CMOS logic circuits; Delay effects; Electrons; Logic programming; Monitoring; PROM; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1985.1156754
