DocumentCode :
387056
Title :
4Mb pseudo/virtually SRAM
Author :
Yoshioka, Shohei ; Nagatomo, Yoshiki ; Takahashi, Satoshi ; Miyamoto, Sadaaki ; Uesugi, Masayuki
Author_Institution :
Oki Electric Industry, Inc., Tokyo, Japan
Volume :
XXX
fYear :
1987
fDate :
0-0 Feb. 1987
Firstpage :
20
Lastpage :
21
Abstract :
This report will discuss a 512K×8 CMOS RAM with two modes of self-refresh operation, The chip utilizes a dynamic buried stacked capacitor memory cell that attains a 40fF storage capacitance in 16.8μm2. The design has an access time of 95ns with refresh operation and is assembled in a 600-mil 32 pin dual in line package.
Keywords :
Automatic control; Bonding; Circuits; Design optimization; Energy consumption; Impedance; Interference; Random access memory; Timing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location :
New York, NY, USA
Type :
conf
DOI :
10.1109/ISSCC.1987.1157228
Filename :
1157228
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=387056
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