DocumentCode
387059
Title
A system-level circuit model for multi- and single-chip CPUs
Author
Bakoglu, H. ; Meindl, J.
Author_Institution
Stanford University, Stanford, CA, USA
Volume
XXX
fYear
1987
fDate
0-0 Feb. 1987
Firstpage
308
Lastpage
309
Abstract
This report will detail a system level circuit model that has been used to predict the performance of microprocessors, gate arrays, and mainframe computers implemented in several IC technologies. Comparisons have been made on the basis of clock frequency, power dissipation and chip/module sizes. Predictions indicate that in ten years a 0.7μm CMOS micro-processor with 6-million transistors will execute 30-60 MIPS.
Keywords
CMOS technology; Clocks; Frequency; Gallium arsenide; Integrated circuit interconnections; Logic devices; Microprocessors; Packaging; Power system modeling; Semiconductor device modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1987.1157231
Filename
1157231
Link To Document