Design of transport triggered architecture processor for discrete cosine transform

The trend in programmable architectures for digital signal processing is to move towards high-level language programming and customizable architectures. Several design methodologies have been proposed for designing application-specific instruction-set processors (ASIP) where the hardware resources are tailored according to the requirements of the application. This paper describes the design of an ASIP for a 32-point discrete cosine transform using the tools from the MOVE framework, which is a semi-automatic design methodology for designing processors that utilize the paradigm of transport triggered architecture. Estimations of the designed processor are obtained on program execution, code size, timing and area.