Rapid system-level performance evaluation and optimization for application mapping onto SoC architectures

System-on-chip (SoC) architectures integrate several heterogeneous components onto a single chip. These components provide various capabilities such as dynamic voltage scaling, reconfiguration, multiple power states, etc., that can be exploited for performance optimization during application design. We propose a generic model (GenM) which captures the capabilities of a large class of SoC architectures and facilitates evaluation and optimization of performance during application design. The GenM model is used as an abstraction to identify various well-defined optimization problems for application mapping onto SoC architectures. Using GenM, we developed an interpretive simulator, High-level Performance Estimator (HiPerE). It integrates component specific performance estimates to rapidly evaluate performance at the system level. The MILAN framework enables hierarchical simulation through the integration of HiPerE and low-level component specific simulators into a unified environment. Hierarchical simulation facilitates efficient design space exploration during application mapping onto SoC architectures.