Title :
Low-power, low-latency global interconnect
Author :
Caputa, Peter ; Svensson, Christer
Author_Institution :
Dept. of Electr. Eng., Linkoping Univ., Sweden
Abstract :
Global interconnects have been identified as a serious limitation to chip scaling, due to their latency and power consumption. We demonstrate a simple scheme to overcome these limitations, based on the utilization of upper-level metals and reduced voltage swing. The upper-level metal allows velocity of light delay if properly dimensioned and power is optimized by an appropriate choice of voltage swing and receiver amplifier.
Keywords :
CMOS integrated circuits; circuit simulation; integrated circuit design; integrated circuit interconnections; integrated circuit metallisation; low-power electronics; CMOS process; chip scaling; circuit simulation; low-power low-latency global interconnects; power consumption; power optimization; receiver amplifier; upper-level metal dimensioning; upper-level metals utilization; velocity of light delay; voltage swing; Capacitance; Delay; Energy consumption; Impedance; Integrated circuit interconnections; Metal-insulator structures; Microstrip; Power amplifiers; Voltage; Wire;
Conference_Titel :
ASIC/SOC Conference, 2002. 15th Annual IEEE International
Print_ISBN :
0-7803-7494-0
DOI :
10.1109/ASIC.2002.1158091
